A tree-systolic array of DLMS adaptive filter

Indexing terms: Maximum driving, Systolic array ABSTRACT In this work, we develop an optimized binary tree-level rule for the design of systolic array structure of Delay LMS (DLMS) adaptive filter Using our developed method higher convergence rate can be obtained without sacriJictng the properties of systolic array structure. Also, based on our optimized tree rule, user can easily design any even-number tap adaptive system with minimum delay and high regularity under the constraints of maximum drtvtng and the total number of taps, effkient implementation of an adaptive filter. It is our motivation to design a rule suitable for chip realization. This paper presents a modified systolic implementation of the DLMS algorithm in which we propose a rule for designer to decide the delay stage (i.e., tree level) and to insert delay element to construct the systolic array suitable for VLSI design. Finally, we verify our systolic array structure via two examples; that is, one is the system identification [7] and the other is adaptive equalizer [2] by computer simulation.